Table of Contents
VLSI Design
Volume 2008, Article ID 160728, 7 pages
Research Article

A Programmable Hardware Cellular Automaton: Example of Data Flow Transformation

Laboratoire Matériaux et Microélectronique de Provence (L2MP-POLYTECH), UMR CNRS 6137, IMT-Technopôle de Château Gombert, Marseille Cedex 20 13451, France

Received 13 April 2007; Accepted 9 December 2007

Academic Editor: Jean-Baptiste Begueret

Copyright © 2008 Samuel Charbouillot et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [5 citations]

The following is the list of published articles that have cited the current article.

  • Edson P. Ferlin, Heitor S. Lopes, Carlos R. Erig Lima, and Maurício Perretto, “PRADA: A high-performance reconfigurable parallel architecture based on the dataflow model,” International Journal of High Performance Systems Architecture, vol. 3, no. 1, pp. 41–55, 2011. View at Publisher · View at Google Scholar
  • Marc Reichenbach, Michael Schmidt, and Dietmar Fey, “Analytical model for the optimization of self-organizing image processing systems utilizing cellular automata,” Proceedings - 2011 14th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops, ISORCW 2011, pp. 162–171, 2011. View at Publisher · View at Google Scholar
  • J. Vazquez Castillo, L. Vela-Garcia, R. Parra-Michel, A. Castillo Atoche, and J. Estrada Lopez, “High-speed low-power parallel random number generator for wireless channel emulators,” 2012 IEEE 3rd Latin American Symposium on Circuits and Systems, LASCAS 2012 - Conference Proceedings, 2012. View at Publisher · View at Google Scholar
  • Joyashree Bag, and Subir Kumar Sarkar, “Development and VLSI implementation of a data security scheme for RFID system using programmable cellular automata,” International Journal of Radio Frequency Identification Technology and Applications, vol. 4, no. 2, pp. 197–211, 2013. View at Publisher · View at Google Scholar
  • Joyashree Bag, Rajanna, and Subir Kumar Sarkar, “Data security for EPC Gen-2: VLSI design and Its FPGA implementation,” International Conference on Advanced Computing and Communication Technologies, ACCT, pp. 330–336, 2013. View at Publisher · View at Google Scholar