Table of Contents Author Guidelines Submit a Manuscript
VLSI Design
Volume 2008 (2008), Article ID 218565, 8 pages
Research Article

Delay Efficient 32-Bit Carry-Skip Adder

Department of Electrical and Computer Engineering, State University of New York, 1 Hawk Dr, New Paltz, NY 12561-2443, USA

Received 27 April 2007; Accepted 9 December 2007

Academic Editor: Jean-Baptiste Begueret

Copyright © 2008 Yu Shen Lin and Damu Radhakrishnan. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


The design of a 32-bit carry-skip adder to achieve minimum delay is presented in this paper. A fast carry look-ahead logic using group generate and group propagate functions is used to speed up the performance of multiple stages of ripple carry adders. The group generate and group propagate functions are generated in parallel with the carry generation for each block. The optimum block sizes are decided by considering the critical path into account. The new architecture delivers the sum and carry outputs in lesser unit delays than existing carry-skip adders. The adder is implemented in 0.25  𝜇 m CMOS technology at 3.3 V. The critical delay for the proposed adder is 3.4 nanoseconds. The simulation results show that the proposed adder is 18 % faster than the current fastest carry-skip adder.