Design and Implementation of a Hardware Module for MIMO Decoding in a 4G Wireless Receiver

<table>BER degradation comparing the floating-point version of the
MIMO decoder (solid lines with marker “o”) and its fixed-point counterpart
implementation Q3 (dashed lines with marker “x”). In the zoomed area, results
for the fixed-point implementation Q2 are also shown for comparison (dotted
lines with marker “<svg height="10.95" id="M172" style="vertical-align:-0.12538pt" version="1.1" viewbox="0 0 28.7875 10.95" width="28.7875" xmlns="http://www.w3.org/2000/svg">
<g transform="matrix(1.25,0,0,-1.25,0,10.95)">
<g transform="translate(72,-63.24)">
<text transform="matrix(1,0,0,-1,-71.95,63.41)">
<tspan style="font-size: 12.50px; " x="0" y="0">1</tspan>
<tspan style="font-size: 12.50px; " x="8.3269978" y="0">d</tspan>
<tspan style="font-size: 12.50px; " x="14.578498" y="0">B</tspan>
</text>
</g>
</g>
</svg>”).</table>

VLSI Design

fig6

Figure 6

Figure 6: Design and Implementation of a Hardware Module for MIMO Decoding in a 4G Wireless Receiver 