Table of Contents
VLSI Design
Volume 2008, Article ID 351962, 10 pages
Research Article

Enabling VLSI Processing Blocks for MIMO-OFDM Communications

1Dipartimento di Elettronica, Informatica e Sistemistica (DEIS), Università degli Studi della Calabria, via P. Bucci, 87036 Rende (CS), Italy
2Dipartimento di Elettronica, Politecnico di Torino, degli Abruzzi 24, 10129 Torino, Italy

Received 30 April 2007; Revised 3 December 2007; Accepted 17 January 2008

Academic Editor: Jean-Baptiste Begueret

Copyright © 2008 Barbara Cerato et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Multi-input multi-output (MIMO) systems combined with orthogonal frequency-division multiplexing (OFDM) gained a wide popularity in wireless applications due to the potential of providing increased channel capacity and robustness against multipath fading channels. However these advantages come at the cost of a very high processing complexity and the efficient implementation of MIMO-OFDM receivers is today a major research topic. In this paper, efficient architectures are proposed for the hardware implementation of the main building blocks of a MIMO-OFDM receiver. A sphere decoder architecture flexible to different modulation without any loss in BER performance is presented while the proposed matrix factorization implementation allows to achieve the highest throughput specified in the IEEE 802.11n standard. Finally a novel 𝐸 8 sphere decoder approach is presented, which allows for the realization of new golden space time trellis coded modulation (GST-TCM) scheme. Implementation cost and offered throughput are provided for the proposed architectures synthesized on a 0.13  𝜇 𝑚 CMOS standard cell technology or on advanced FPGA devices.