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VLSI Design
Volume 2008, Article ID 512946, 8 pages
http://dx.doi.org/10.1155/2008/512946
Research Article

A Phase-Locked Loop with 30% Jitter Reduction Using Separate Regulators

Department of Electrical Engineering, National Sun Yat-Sen University, 70 Lian-Hai Road, Kaohsiung 80424, Taiwan

Received 28 January 2008; Revised 3 July 2008; Accepted 31 July 2008

Academic Editor: Wieslaw Kuzmicz

Copyright © 2008 Tzung-Je Lee and Chua-Chin Wang. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. U. Ladebusch and C. A. Liss, “Terrestrial DVB (DVB-T): a broadcast technology for stationary portable and mobile use,” Proceedings of the IEEE, vol. 94, no. 1, pp. 183–193, 2006. View at Publisher · View at Google Scholar
  2. F. Herzel and B. Razavi, “A study of oscillator jitter due to supply and substrate noise,” IEEE Transactions on Circuits and Systems II, vol. 46, no. 1, pp. 56–62, 1999. View at Publisher · View at Google Scholar
  3. M. Ei-Hage and F. Yuan, “An overview of low-voltage VCO delay cells and a worst-case analysis of supply noise sensitivity,” in Proceedings of the Canadian Conference on Electrical and Computer Engineering (CCECE '04), vol. 3, pp. 1785–1788, Niagara Falls, Canada, May 2004.
  4. J. M. Ingino and V. R. von Kaenel, “A 4-GHz clock system for a high-performance system-on-a-chip design,” IEEE Journal of Solid-State Circuits, vol. 36, no. 11, pp. 1693–1698, 2001. View at Publisher · View at Google Scholar
  5. J. G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques,” IEEE Journal of Solid-State Circuits, vol. 31, no. 11, pp. 1723–1732, 1996. View at Publisher · View at Google Scholar
  6. K. M. Ring and S. Krishnan, “Long-term jitter reduction through supply noise compensation,” in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS '08), pp. 2382–2385, Seattle, Wash, USA, May 2008. View at Publisher · View at Google Scholar
  7. Y. Chen, Z. Wang, and L. Zhang, “A 5 GHz 0.18-μm CMOS technology PLL with a symmetry PFD,” in Proceedings of the International Conference on Microwave and Millimeter Wave Technology (ICMMT '08), vol. 2, pp. 562–565, Nanjing, China, April 2008. View at Publisher · View at Google Scholar
  8. X. Fan, C. Mishra, and E. Sánchez-Sinencio, “Single miller capacitor frequency compensation technique for low-power multistage amplifiers,” IEEE Journal of Solid-State Circuits, vol. 40, no. 3, pp. 584–592, 2005. View at Publisher · View at Google Scholar
  9. H. Kondoh, H. Notani, T. Yoshimura, H. Shibata, and Y. Matsuda, “1.5-V 250-MHz to 3.0-V 622-MHz operation CMOS phase-locked loop with precharge type phase-frequency detector,” IEICE Transactions on Electronics, vol. E78-C, no. 4, pp. 381–388, 1995. View at Google Scholar
  10. C. Toumazou, G. S. Moschytz, and B. Gilbert, Eds., Trade-Offs in Analog Circuit Design, Kluwer Academic Publishers, Reading, Mass, USA, 2002.
  11. W. Rhee, “Design of high-performance CMOS charge pumps in phase-locked loops,” in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS '99), vol. 2, pp. 545–548, Orlando, Fla, USA, May-June 1999. View at Publisher · View at Google Scholar
  12. S.-R. Han, C.-N. Chuang, and S.-I. Liu, “A time-constant calibrated phase-locked loop with a fast-locked time,” IEEE Transactions on Circuits and Systems II, vol. 54, no. 1, pp. 34–37, 2007. View at Publisher · View at Google Scholar