Table of Contents
VLSI Design
Volume 2008, Article ID 517919, 10 pages
http://dx.doi.org/10.1155/2008/517919
Research Article

Fine Control of Local Whitespace in Placement

1Department of EECS, University of Michigan, 2260 Hayward Avenue, Ann Arbor, MI 48109-2121, USA
2IBM Austin Research Lab, IBM Corporation, 11501 Burnet Road, Austin, TX 78758, USA

Received 1 November 2007; Revised 16 May 2008; Accepted 4 August 2008

Academic Editor: Spyros Tragoudas

Copyright © 2008 Jarrod A. Roy et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

In modern design methodologies, a large fraction of chip area during placement is left unused by standard cells and allocated as “whitespace.” This is done for a variety of reasons including the need for subsequent buffer insertion, as a means to ensure routability, signal integrity, and low coupling capacitance between wires, and to improve yield through DFM optimizations. To this end, layout constraints often require a certain minimum fraction of whitespace in each region of the chip. Our work introduces several techniques for allocation of whitespace in global, detail, and incremental placement. Our experiments show how to efficiently improve wirelength by reallocating whitespace in legal placements at the large scale. Additionally, for the first time in the literature, we empirically demonstrate high-precision control of whitespace in designs with macros and obstacles. Our techniques consistently improve the quality of whitespace allocation of top-down as well as analytical placement methods and achieve low penalties on designs from the ISPD 2006 placement contest with minimal interconnect increase.