Table of Contents
VLSI Design
Volume 2008, Article ID 596146, 9 pages
Research Article

Choice of a High-Level Fault Model for the Optimization of Validation Test Set Reused for Manufacturing Test

1Grenoble Institute of Technology (LCIS), 50 Rue B. de Laffemas, BP54, 26092 Valence Cedex 9, France
2STMicroelectronics, 850 Rue Jean Monnet, 38926 Crolles Cedex, France

Received 11 October 2007; Accepted 9 April 2008

Academic Editor: Bozena Kaminska

Copyright © 2008 Yves Joannon et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


With the growing complexity of wireless systems on chip integrating hundreds-of-millions of transistors, electronic design methods need to be upgraded to reduce time-to-market. In this paper, the test benches defined for design validation or characterization of AMS & RF SoCs are optimized and reused for production testing. Although the original validation test set allows the verification of both design functionalities and performances, this test set is not well adapted to manufacturing test due to its high execution time and high test equipment costs requirement. The optimization of this validation test set is based on the evaluation of each test vector. This evaluation relies on high-level fault modeling and fault simulation. Hence, a fault model based on the variations of the parameters of high abstraction level descriptions and its related qualification metric are presented. The choice of functional or behavioral abstraction levels is discussed by comparing their impact on structural fault coverage. Experiments are performed on the receiver part of a WCDMA transceiver. Results show that for this SoC, using behavioral abstraction level is justified for the generation of manufacturing test benches.