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VLSI Design
Volume 2008 (2008), Article ID 610420, 9 pages
http://dx.doi.org/10.1155/2008/610420
Research Article

An FFT Core for DVB-T/DVB-H Receivers

Department of Electronic and Communication, CEIT and Tecnun, University of Navarra, 20018 Donostia-San Sebastian, Spain

Received 27 April 2007; Revised 15 November 2007; Accepted 23 January 2008

Academic Editor: Jean-Baptiste Begueret

Copyright © 2008 A. Cortés et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

This paper presents the design and implementation of a 2K/4K/8K multiple mode FFT core for DVB-T/DVB-H receivers. The proposed core is based on a pipeline radix-22 SDF architecture. The necessary changes in the radix-22 SDF architecture to achieve an efficient FFT implementation are detailed. Quantization effects and timing design parameters are analyzed for DVB-T/DVB-H. Area and power results are provided for the proposed core.