Table of Contents
VLSI Design
Volume 2008, Article ID 890410, 8 pages
Research Article

Fully Pipelined Parallel Architecture for Candidate Block and Pixel-Subsampling-Based Motion Estimation

School of Electronics and Communication Engineering (ECE), Anna University, Chennai-600 025, Tamil Nadu, India

Received 7 May 2007; Revised 26 September 2007; Accepted 2 January 2008

Academic Editor: Mohab Anis

Copyright © 2008 Reeba Korah and J.Raja Paul Perinbam. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


This paper presents a low power and high speed architecture for motion estimation with Candidate Block and Pixel Subsampling (CBPS) Algorithm. Coarse-to-fine search approach is employed to find the motion vector so that the local minima problem is totally eliminated. Pixel subsampling is performed in the selected candidate blocks which significantly reduces computational cost with low quality degradation. The architecture developed is a fully pipelined parallel design with 9 processing elements. Two different methods are deployed to reduce the power consumption, parallel and pipelined implementation and parallel accessing to memory. For processing 30 CIF frames per second our architecture requires a clock frequency of 4.5 MHz.