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VLSI Design
Volume 2008, Article ID 890410, 8 pages
http://dx.doi.org/10.1155/2008/890410
Research Article

Fully Pipelined Parallel Architecture for Candidate Block and Pixel-Subsampling-Based Motion Estimation

School of Electronics and Communication Engineering (ECE), Anna University, Chennai-600 025, Tamil Nadu, India

Received 7 May 2007; Revised 26 September 2007; Accepted 2 January 2008

Academic Editor: Mohab Anis

Copyright © 2008 Reeba Korah and J.Raja Paul Perinbam. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Reeba Korah and J.Raja Paul Perinbam, “Fully Pipelined Parallel Architecture for Candidate Block and Pixel-Subsampling-Based Motion Estimation,” VLSI Design, vol. 2008, Article ID 890410, 8 pages, 2008. https://doi.org/10.1155/2008/890410.