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VLSI Design
Volume 2008, Article ID 890410, 8 pages
http://dx.doi.org/10.1155/2008/890410
Research Article

Fully Pipelined Parallel Architecture for Candidate Block and Pixel-Subsampling-Based Motion Estimation

School of Electronics and Communication Engineering (ECE), Anna University, Chennai-600 025, Tamil Nadu, India

Received 7 May 2007; Revised 26 September 2007; Accepted 2 January 2008

Academic Editor: Mohab Anis

Copyright © 2008 Reeba Korah and J.Raja Paul Perinbam. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. A. Artieri and F. Jutand, “A versatile and powerful chip for real time motion estimation,” in Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP '89), vol. 4, pp. 2453–2456, Glasgow, UK, May 1989. View at Publisher · View at Google Scholar
  2. C.-M. Wu and D.-K. Yeh, “A VLSI motion estimator for video image compression,” IEEE Transactions on Consumer Electronics, vol. 39, no. 4, pp. 837–846, 1993. View at Publisher · View at Google Scholar
  3. F.-M. Yang, S. Wolter, and R. Laur, “VLSI architecture for HDTV motion estimation based on block-matching algorithm,” in Proceedings of the 7th International Conference on VLSI Design, pp. 287–290, Calcutta, India, January 1994. View at Publisher · View at Google Scholar
  4. N. Roma and L. Sousa, “Efficient and configurable full-search block matching processors,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 12, no. 12, pp. 1160–1167, 2002. View at Publisher · View at Google Scholar
  5. M. Abbas, B. Talha, S. Khan, and A. Abbas, “A motion estimation chip for block based MPEG-4 video applications,” in Proceedinga of the 7th International Multi Topic Conference (INMIC '03), pp. 253–257, Islamabad, Pakistan, December 2003. View at Publisher · View at Google Scholar
  6. M. Sayed and W. Badawy, “A fully parallel-pipelined architecture for full-search block-based motion estimation,” in Proceedings of the 14th International Conference on Microelectronics (ICM '02), pp. 24–27, Beirut, Lebanon, December 2002.
  7. L. De Vos and M. Schobinger, “Efficient architecture of a programmable block matching algorithm,” in Proceedings of the International Conference on Application-Specific Array Processors, pp. 560–571, Venice, Italy, October 1993. View at Publisher · View at Google Scholar
  8. Y.-K. Lai and L.-G. Chen, “A data-interlacing architecture with two-dimensional data-reuse for full-search block matching algorithm,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 8, no. 2, pp. 124–127, 1998. View at Publisher · View at Google Scholar
  9. D. Xu, R. Gao, and H. Batatia, “An improved parallel architecture for MPEG-4 motion estimation in 3G mobile applications,” in roceedings of IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '03), vol. 2, pp. 689–692, Hong kong, April 2003. View at Publisher · View at Google Scholar
  10. S.-H. Wang, W.-L Tao, C.-N. Wang, W.-H. Pong, and H. Chiang, “Platform based design of all binary motion estimation (ABME) with bus interleaved architecture,” in Proceedings of International Symposium on VLSI Design, Automation and Test (VLSI-TSA-DAT '05), pp. 241–244, Hsinchu, Taiwan, April 2005. View at Publisher · View at Google Scholar
  11. R. Korah and J. R. P. Perinbam, “A novel coarse-to-fine search motion estimator,” Information Technology Journal, vol. 5, no. 6, pp. 1073–1077, 2006. View at Google Scholar
  12. B. Liu and A. Zaccarin, “New fast algorithms for the estimation of block motion vectors,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 3, no. 2, pp. 148–157, 1993. View at Publisher · View at Google Scholar