Floorplan-Driven Multivoltage High-Level Synthesis

<table class="table-group" id="tab5"><tr><td><table class="table"><tr><td class="thead-hr" colspan="4"><hr/></td></tr><tr class="thead"><td align="left">Resource</td><td align="center">Multiplier</td><td align="center">ALU</td><td align="center">Register</td></tr><tr><td class="thead-hr" colspan="4"><hr/></td></tr><tr><td align="left" rowspan="2">Dimensions</td><td align="center"><span style="width: 42.137501px;"><svg height="11.125" id="M39" style="vertical-align:-0.1638pt" version="1.1" viewbox="0 0 42.137501 11.125" width="42.137501" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
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VLSI Design

tab5

Table 5

Table 5: Floorplan-Driven Multivoltage High-Level Synthesis 