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VLSI Design
Volume 2009, Article ID 283702, 14 pages
http://dx.doi.org/10.1155/2009/283702
Review Article

Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow-Power Applications

Semiconductor Devices and VLSI Technology (SDVT) Group, Department of Electronics & Computer Engineering (E & CE), Indian Insititue of Technology (IIT), Roorkee, Roorkee-247667, Uttarakhand, India

Received 13 August 2008; Revised 21 November 2008; Accepted 21 January 2009

Academic Editor: Mohamed Masmoudi

Copyright © 2009 Ramesh Vaddi et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [23 citations]

The following is the list of published articles that have cited the current article.

  • Manash Chanda, Jeet Basak, Diptansu Sinha, Tanushree Ganguli, and Chandan K. Sarkar, “Comparative analysis of adiabatic logics in sub-threshold regime for ultra-low power application,” 2016 Conference on Emerging Devices and Smart Systems (ICEDSS), pp. 37–41, . View at Publisher · View at Google Scholar
  • S. K. Tripathi, Mohd. Samar Ansari, and Iqbal A. Khan, “Performance Comparison of a Current Conveyor in 0.35 μm & 65 nm CMOS and 32 nm CNFET,” 2014 International Conference on Devices, Circuits and Communications (ICDCCom), pp. 1–5, . View at Publisher · View at Google Scholar
  • Vandana Niranjan, Ashwni Kumar, and Shail Bala Jain, “Triple well subthreshold CMOS logic using body-bias technique,” 2013 IEEE International Conference on Signal Processing, Computing and Control (ISPCC), pp. 1–6, . View at Publisher · View at Google Scholar
  • Mohd Shamian Zainal, Shingo Yoshizawa, and Yoshikazu Miyanaga, “Optimal power reduction on wireless OFDM receiver,” 2010 IEEE Region 8 International Conference on Computational Technologies in Electrical and Electronics Engineering (SIBIRCON), pp. 263–267, . View at Publisher · View at Google Scholar
  • R.D. Jorgenson, L. Sorensen, D. Leet, M.S. Hagedorn, D.R. Lamb, T.H. Friddell, and W.P. Snapp, “Ultralow-Power Operation in Subthreshold Regimes Applying Clockless Logic,” Proceedings of the IEEE, vol. 98, no. 2, pp. 299–314, 2010. View at Publisher · View at Google Scholar
  • Ashutosh Nandi, and Rajeevan Chandel, “Design and analysis of sub-DT sub-domino logic circuits for ultra low power applications,” Journal of Low Power Electronics, vol. 6, no. 4, pp. 513–520, 2010. View at Publisher · View at Google Scholar
  • Hermann Kopetz, “Energy-saving mechanisms in the time-triggered architecture,” ISORC 2010 - 2010 13th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, vol. 1, pp. 28–33, 2010. View at Publisher · View at Google Scholar
  • Mawahib Hussein Sulieman, Valeriu Beiu, and Walid Ibrahim, “Low-power and highly reliable logic gates transistor-level optimizations,” 2010 10th IEEE Conference on Nanotechnology, NANO 2010, pp. 254–257, 2010. View at Publisher · View at Google Scholar
  • Vandana Niranjan, Maneesha Gupta, and Nupur Pzakash, “Subthreshold Schmitt trigger using body-bias technique for ultra low power and high performance applications,” Russian Microelectronics, vol. 40, no. 2, pp. 141–145, 2011. View at Publisher · View at Google Scholar
  • Kyungseok Kim, and Vishwani D. Agrawal, “Ultra low energy CMOS logic using below-threshold dual-voltage supply,” Journal of Low Power Electronics, vol. 7, no. 4, pp. 460–470, 2011. View at Publisher · View at Google Scholar
  • Mohd Hasan, and Pable, “Performance optimization of CNFET for ultra-low power reconfigurable architecture,” ACM International Conference Proceeding Series, pp. 215–220, 2011. View at Publisher · View at Google Scholar
  • Mohd Hasan, and Pable, “Performance analysis of FPGA interconnect fabric for ultra-low power applications,” ACM International Conference Proceeding Series, pp. 210–214, 2011. View at Publisher · View at Google Scholar
  • Kyungseok Kim, and Vishwani D. Agrawal, “True minimum energy design using dual below-threshold supply voltages,” Proceedings of the IEEE International Conference on VLSI Design, pp. 292–297, 2011. View at Publisher · View at Google Scholar
  • Subhra Dhar, Manisha Pattanaik, and Rajaram, “Evaluating pathways for optimised subthreshold design: Scaled bulk nMOSFETs in deep and ultradeep submicron region,” Journal of Computational and Theoretical Nanoscience, vol. 9, no. 3, pp. 401–408, 2012. View at Publisher · View at Google Scholar
  • Vishal Kothari, Manisha Pattanaik, Subhra Dhar, and P. Rajaram, “Effective Techniques for Optimized Subthreshold Design Using Symmetric Double Gate MOSFET,” Journal Of Computational And Theoretical Nanoscience, vol. 9, no. 12, pp. 2160–2165, 2012. View at Publisher · View at Google Scholar
  • S.D. Pable, and Mohd. Hasan, “A novel robust FPGA routing switch box design for ultra low power applications,” International Journal of Electronics, vol. 99, no. 1, pp. 15–27, 2012. View at Publisher · View at Google Scholar
  • Rajni Gautam, Manoj Saxena, R. S. Gupta, and Mridula Gupta, “Analytical Model of Double Gate MOSFET for High Sensitivity Low Power Photosensor,” Journal of Semiconductor Technology and Science, vol. 13, no. 5, pp. 500–510, 2013. View at Publisher · View at Google Scholar
  • Subhra Dhar, Manisha Pattanaik, and P. Rajaram, “Analysing ION/IOFF in ultradeep-submicron CMOS devices using grooved nMOSFETs for low-power applications,” International Journal of Signal and Imaging Systems Engineering, vol. 6, no. 1, pp. 24–30, 2013. View at Publisher · View at Google Scholar
  • Azzedin Es-Sakhi, and Masud H. Chowdhury, “Silicon on ferroelectric insulator field effect transistor (SOF-FET) for ultra low power design,” Midwest Symposium on Circuits and Systems, pp. 77–80, 2013. View at Publisher · View at Google Scholar
  • Azzedin D. Es-Sakhi, and Masud H. Chowdhury, “Analysis of the current-voltage characteristics of Silicon on Ferroelectric Insulator Field Effect Transistor (SOF-FET),” International System on Chip Conference, pp. 152–155, 2014. View at Publisher · View at Google Scholar
  • Tripathi, and Mohd. Samar Ansari, “Voltage-mode universal filter for ZigBee using ±0.9V 32nm CNFET ICC-II,” Proceedings of the 5th International Conference on Confluence 2014: The Next Generation Information Technology Summit, pp. 471–475, 2014. View at Publisher · View at Google Scholar
  • Ajit Palpp. 1–389, 2015. View at Publisher · View at Google Scholar
  • Eryk Dutkiewicz, Meriam Gay Bautista, and Michael Heimlich, “Subthreshold energy harvesters circuits for biomedical implants applications,” EAI Endorsed Transactions on Energy Web, vol. 16, no. 9, 2016. View at Publisher · View at Google Scholar