Device and Circuit Design Challenges in the Digital Subthreshold 
                        Region for Ultralow-Power Applications

<table><svg height="15.4375" id="M106" style="vertical-align:-3.41936pt" version="1.1" viewbox="0 0 25.799999 15.4375" width="25.799999" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
<g transform="matrix(.017,-0,0,-.017,.062,11.112)"><path d="M414 650l-6 -28q-63 -4 -78.5 -17.5t-27.5 -71.5l-77 -416q-11 -58 0.5 -71.5t77.5 -17.5l-5 -28h-275l8 28q63 4 79.5 18.5t27.5 70.5l80 416q11 57 -2 71t-81 18l6 28h273z" id="x1D43C"></path></g>
<g transform="matrix(.012,-0,0,-.012,7.487,15.187)"><path d="M381 665q131 0 226.5 -93t95.5 -239q0 -158 -96 -253t-238 -95q-137 0 -231 95t-94 238q0 142 92.5 244.5t244.5 102.5zM359 629q-89 0 -151 -74.5t-62 -208.5q0 -141 69 -233t175 -92q90 0 150.5 74t60.5 211q0 152 -69 237.5t-173 85.5z" id="x4F"></path></g><g transform="matrix(.012,-0,0,-.012,16.281,15.187)"><path d="M719 650v-28q-43 -2 -62 -15t-22 -44q-6 -47 -6 -169v-403h-31l-426 524h-2v-251q0 -111 6 -169q4 -37 24 -50.5t72 -16.5v-28h-237v28q45 2 64.5 16t23.5 49q6 62 6 171v220q0 54 -3 68.5t-17 32.5q-16 19 -34.5 26.5t-54.5 10.5v28h147l418 -502h3v246q0 117 -7 166
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</svg>  and <i>S</i> versus gate length [<a href="/journals/vlsi/2009/283702/#B13">13</a>].</table>

VLSI Design

fig6

Figure 6

Figure 6: Device and Circuit Design Challenges in the Digital Subthreshold 
                        Region for Ultralow-Power Applications 

VLSI Design

Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow-Power Applications

Figure 6