Table of Contents
VLSI Design
Volume 2009, Article ID 679853, 7 pages
http://dx.doi.org/10.1155/2009/679853
Research Article

Reduced Voltage Scaling in Clock Distribution Networks

Department of Electrical and Computer Engineering, University of Texas at San Antonio, San Antonio, TX 78249, USA

Received 28 April 2009; Accepted 18 December 2009

Academic Editor: Xianlong Long Hong

Copyright © 2009 Khader Mohammad et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. N. Magen, A. Kolodny, U. Weiser, and N. Shamir, “Interconnect-power dissipation in a microprocessor,” in Proceedings of the International Workshop on System Level Interconnect Prediction (SLIP '04), pp. 7–13, Februery 2004. View at Scopus
  2. S. K. H. Fung, H. T. Huang, S. M. Cheng et al., “65nm CMOS high speed, general purpose and low power transistor technology for high volume foundry application,” in Proceedings of the Digest of Technical Papers Symposium on VLSI Technology, pp. 92–93, June 2004.
  3. F. Haj and M. Sachdev, “A low-power reduced swing global clocking methodology,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 5, pp. 538–545, 2004. View at Publisher · View at Google Scholar · View at Scopus
  4. H. Zhang, V. George, and J. M. Rabaey, “Low-swing on-chip signaling techniques: effectiveness and robustness,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 8, no. 3, pp. 264–272, 2000. View at Publisher · View at Google Scholar
  5. “Typical HSPICE model files,” http://ptm.asu.edu/.
  6. P.-F. Lu, L. Sigal, N. Cao, P. Woltgens, R. Robertazzi, and D. Heidel, “A low-voltage swing latch for reduced power dissipation in high-frequency microprocessors,” in Proceedings of the IEEE International SOI Conference, pp. 165–167, October 2004.
  7. A. D. Bailey, J. Di, S. C. Smith, and H. A. Mantooth, “Ultra-low power delay-insensitive circuit design,” in Proceedings of the IEEE Midwest Symposium on Circuits and Systems, pp. 503–506, 2008. View at Publisher · View at Google Scholar
  8. S. Lin, Y.-B. Kim, and F. Lombardi, “A 32nm SRAM design for low power and high stability,” in Proceedings of the IEEE Midwest Symposium on Circuits and Systems, pp. 422–425, 2008. View at Publisher · View at Google Scholar
  9. J. Yuan and C. Svensson, “New single-clock CMOS latches and flipflops with improved speed and power savings,” IEEE Journal of Solid-State Circuits, vol. 32, no. 1, pp. 62–69, 1997. View at Google Scholar