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VLSI Design
/
2009
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Article
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Tab 2
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Research Article
Reduced Voltage Scaling in Clock Distribution Networks
Table 2
Comparison of a clock spine with FVS or RVS clock buffers.
Delay (ps)
Slew Rate (ps)
Power (mW)
FVS
185
4
3.709
RVS
201
5.2
2.7