VLSI Design

VLSI Design / 2009 / Article / Tab 1

Research Article

Networks-On-Chip Based on Dynamic Wormhole Packet Identity Mapping Management

Table 1

Synthesis results of the routers on a Virtex2 FPGA device (flit size:  bits, FIFO buffer depth: 8).


Number of slices48845009501650175114
Max. freq. (MHz)83.3991.0289.4388.57100.51

We are committed to sharing findings related to COVID-19 as quickly and safely as possible. Any author submitting a COVID-19 paper should notify us at help@hindawi.com to ensure their research is fast-tracked and made available on a preprint server as soon as possible. We will be providing unlimited waivers of publication charges for accepted articles related to COVID-19. Sign up here as a reviewer to help fast-track new submissions.