Post-CTS Delay Insertion

Figure 5

A sample reconvergent path system. Clock delays $t_d$ and $t_c$ satisfy the timing of paths $R_d\to R_1\text{,}$$R_1\to R_2\text{,}$$R_2\to R_c$. However, the timing of one or both of paths $R_d\to R_3\text{,}$$R_3\to R_c$ is violated.