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VLSI Design
/
2010
/
Article
/
Tab 3
/
Research Article
Post-CTS Delay Insertion
Table 3
LP model for post-CTS delay insertion method.
Minimize inserted buffer delay
min
T
s.t.
t
i
+
Δ
i
+
D
CQ
i
+
D
P
Max
i
f
≤
t
f
+
Δ
f
+
T
-
S
j
t
i
+
Δ
i
+
D
CQ
i
+
D
P
Min
i
f
≥
t
f
+
Δ
f
+
H
f
Δ
i
≤
k
1
T
z
s
∑
i
=
0
N
-
1
Δ
i
≤
k
2
T
z
s
N