Error Immune Logic for Low-Power Probabilistic Computing

Figure 2

The probability of output error $\delta$, of a NAND versus an XOR when a probability error of $ϵ=0.2$ is present at the input. Further, $\delta$ is compared for a full-adder implemented with NAND-NAND and with a standard XOR when $ϵ=0.2$ is present at the input. Note that not only is the probability of output error $\delta$ much lower for a NAND gate than an XOR gate, but that the error propagated from the NAND is improved over the input error. In a sense, a NAND “heals” the circuit. Note that the gate itself does not compute erroneously in this example.