Error Immune Logic for Low-Power Probabilistic Computing

Table 2

Single-Bit Flips (SBF) at the input that could cause a flip in the output of the carryout calculation of a dual-rail asynchronous adder.

$A$	$B$	$C$	$A_t$	$A_f$	$B_t$	$B_f$	$C_t$	$\overline{C\text{ou}{\text{t}}_t}$	SBF Error
$\varnothing$	$\varnothing$	$\varnothing$	0	0	0	0	0	1	$\varnothing$
0	0	0	0	1	0	1	0	1	$\varnothing$
0	0	1	0	1	0	1	1	1	$A_t$,$B_t$
0	1	0	0	1	1	0	0	1	$C_t$
0	1	1	0	1	1	0	1	0	$C_t$
1	0	0	1	0	0	1	0	1	$C_t$,$B_t$
1	0	1	1	0	0	1	1	0	$C_t$,$A_t$
1	1	0	1	0	1	0	0	0	$B_t$,$A_t$
1	1	1	1	0	1	0	1	0	$\varnothing$