FPGA-Based Software Implementation of Series Harmonic Compensation for Single Phase Inverters

Table 3

Resource utilization of the Simple Observer (SO) and Composite Observer (CO) Control scheme using Quartus II tool.

	SO	CO
Family	Cyclone II	Cyclone II
Device	EP2C8T144C8	EP2C8T144C8
Total logic elements	1,779/8,256 (21%)	5,517/8,256 (66%)
Combinational with no register	1448	4981
Register only	16	13
Combinational with a register	315	523
Logic element usage by number of LUT inputs
4 input functions	215	662
3 input functions	1207	3967
<=2 input functions	341	875
Register only	16	13
Combinational cells for routing	13	32
Logic elements by mode
Normal mode	574	1480
Arithmetic mode	1189	4024
Total registers	331/8,256 (4%)	536/8,256 (6%)
Total LABs	158/516(30%)	452/516 (87%)
Total pins	9/85 (10%)	9/85 (10%)
M4Ks	2/36 (5%)	2/36 (5%)
Total memory bits	5,120/165,888 (3%)	5,120/165,888 (3%)
Total RAM block bits	9,216/165,888 (5%)	9,216/165,888 (5% )
Embedded Multiplier 9-bit elements	36/36 (100%)	36/36 (100%)