An Approach for Implementing State Machines with Online Testability

<table>Implementation of circuit to generate <math id="M62" xmlns="http://www.w3.org/1998/Math/MathML"><mrow><msub><mrow><mi>F</mi></mrow><mrow><mn>1</mn></mrow></msub></mrow></math> and <math id="M63" xmlns="http://www.w3.org/1998/Math/MathML"><mrow><msubsup><mrow><mi>F</mi></mrow><mrow><mn>1</mn></mrow><mrow><mi>′</mi></mrow></msubsup></mrow></math>.</table>

VLSI Design

fig6

Figure 6

Figure 6: An Approach for Implementing State Machines with Online Testability 