A novel Capacitor array structure for Successive Approximation Register (SAR) ADC is proposed. This circuit efficiently utilizes charge recycling to achieve high-speed of operation and it can be applied to high-speed and low-to-medium-resolution SAR ADC. The parasitic effects and the static linearity performance, namely, the INL and DNL, of the proposed structure are theoretically analyzed and behavioral simulations are performed to demonstrate its effectiveness under those nonidealities. Simulation results show that to achieve the same conversion performance the proposed capacitor array structure can reduce the average power consumed from the reference ladder by 90% when compared to the binary-weighted splitting capacitor array structure.

1. Introduction

The SAR ADC is widely used in many communication systems, such as ultra-wideband (UWB) and wireless sensor networks which require low-to-medium-resolution converters with low power consumption. Traditional SAR ADCs are difficult to be applied in high-speed design; however the improvement of technologies and design methods have allowed the implementation of high-speed, low-power SAR ADCs that become consequently more attractive for a wide variety of applications [1, 2].

The power dissipation in an SAR converter is dominated by the reference ladder of the DAC capacitor array. Recently, a capacitor splitting technique has been presented, which was proven to use 31% less power from the reference voltage and achieve better DNL than the binary-weighted capacitor (BWC) array. The total power consumption of a 5 b binary-weighted split capacitor (BWSC) array is 6 mW which does not take into account the power from the reference ladder [3]. However, as the resolution increases, the total number of input capacitance in the binary-scaled capacitive DAC will cause an exponential increase in power dissipation as well as a limitation with reduction of speed due to a large charging time-constant. Therefore, small capacitance spread for DAC capacitor arrays is highly desirable in high-speed SAR ADCs [4].

This paper presents a novel structure of a split capacitor array for optimization of the power efficiency and the speed of SAR ADCs. Due to the series combination of the split capacitor array both small capacitor ratios and power-efficient charge recycling in the DAC capacitor array can be achieved, leading to fast DAC settling time and low power dissipation in the SAR ADC. The parasitic effects, the position of the attenuation capacitor, as well as the linearity performance (INL and DNL) of the proposed structure will be theoretically discussed and behavioral simulations will be performed. Different from the BWSC array, which only achieves better DNL (but not INL) than the BWC array, the proposed capacitor array structure can have both better INL and DNL than the series capacitor (SC) array. The design and simulations of an 8 b 180-MS/s SAR ADC in 1.2-V supply voltage are presented in 90 nm CMOS exhibiting a Signal-to-Noise-and-Distortion Ratio (SNDR) of 48 dB, with a total power consumption of 14 mW which demonstrates the feasibility of the proposed structure.

2. The Overall SAR ADC Operation

The architecture of an SAR ADC is shown in Figure 1, consisting of a series structure of a capacitive DAC, a comparator, and successive approximation (SA) control logic. The SA control logic includes shift registers and switch drivers which control the DAC operation by performing the binary-scaled feedback during the successive approximation. The DAC capacitor array is the basic structure of the SAR ADC and it serves both to sample the input signal and as a DAC for creating and subtracting the reference voltage.

3. Capacitor Array Structure

3.1. Capacitor Structure Design

The major limitation on the speed of the SA converter is often related with the RC time constants of the capacitor array, reference ladder, and switches. For a BWC array the size of capacitors rises exponentially with the resolution in number of bits, which causes large power and RC settling time, thus limiting the speed of the overall SAR ADC. To solve this problem, Figure 2(a) shows an SC array [5], which utilizes attenuation capacitors 𝐶atten to separate the capacitive DAC into 𝑏𝑀 bits MSB and 𝑏𝐿 bits LSB arrays. Thus, smaller capacitor ratios can be achieved when compared to the BWC array. However, charge-redistribution switching method for the SC array has been proven to be inefficient when discharging the MSB capacitor and charging the MSB/2 capacitor, which consumes 5 times more power than the charge-recycling switching method. Thus, a series-split capacitor (SSC) array is proposed, as shown in Figure 2(b), which can both alleviate the speed limitation and implement a charge-recycling switching approach.

The solution to perform charge-recycling for SC array is different from the BWC array, which just splits the MSB capacitor 𝐶MSB into 𝑛1 subarrays. As illustrated in Figure 2(b), the 𝐶MSB of the SC array is split into 𝑏𝑀1 subarrays in the MSB array, where the total capacitance of the 𝑏𝑀-1 subarrays is 𝐶MSB𝐶0 and as a result the capacitors in LSB array and 𝐶atten should be doubled; thus the 𝐶eq can be calculated as

𝐶eq=2𝐶atten//𝐶totalLSB=2𝐶0,𝐶totalLSB=2𝑏𝐿+1𝐶0,𝐶totalMSB=𝑏𝑀1𝑛=12𝑛𝐶0,(1) where 𝐶totalLSB and 𝐶totalMSB are the sum of LSB and MSB array capacitors, respectively. The 𝐶eq can then be seen as two split unit capacitors 𝐶0 attached to the right side of MSB array to maintain the capacitive ratio as 2𝑏𝑀2211. Therefore, the charge-recycling methodology in each section can perform binary-scaled feedback during the successive approximation.

3.2. Charge Recycling Implementation

In the proposed implementation the series-split capacitor array is designed to achieve charge recycling for the 𝑛 (𝑛=𝑏𝑀+𝑏𝐿+1) bit capacitive DAC, as shown in Figure 2(b). During the global sampling phase, the voltage 𝑉in is stored in the entire capacitor array. Then, the algorithmic conversion begins by switching all upper capacitor arrays to 𝑉ref and the lower to 𝑉ref, respectively, instead of switching only the MSB capacitor to 𝑉ref and others to 𝑉ref. This implies that in the conversion phase 1 (corresponding to MSB capacitor conversion) 𝑉out settles to (considering only differential node voltage)

𝑉out[1]=𝑉in+𝑉ref2𝑉ref2=𝑉in,(2) and the comparator output will be

𝐷1=1,𝑉in>0,1,𝑉in<0.(3) The comparator output will decide the switching logic of 𝑆𝑏𝑀+𝑏𝐿1,1 and 𝑆𝑏𝑀+𝑏𝐿1,2. If 𝐷1 is low, 𝑆𝑏𝑀+𝑏𝐿1,1 is switched to 𝑉ref, dropping the voltage at 𝑉out[2] to 𝑉in𝑉ref/2. If 𝐷1 is high, 𝑆𝑏𝑀+𝑏𝐿1,2 is switched to 𝑉ref, raising the voltage at 𝑉out[2] to 𝑉in+𝑉ref/2. The above process is repeated for 𝑛1 cycles. As 𝑆𝑏𝑀+𝑏𝐿1,1 is switched from 𝑉ref to 𝑉ref (bit decision back from “1” to “0”) the switches, from 𝑆0,1 to 𝑆𝑏𝑀+𝑏𝐿2,1, are kept connected to 𝑉ref and drive 𝑉out[1] to 𝑉out[2]. The initial charge, supplied by 𝑉ref in phase 1, is kept stored in the capacitors which will connect to 𝑉ref at phase 1, instead of being redistributed; so the charge formed at phase 1 can be recycled in the next 𝑛1 phases. However, the conventional switching method that discharges MSB capacitor and charges the MSB/2 capacitor will cause charge redistribution in the capacitor array and thus consuming more power.

3.3. Linearity Performance

To analyze the linearity of the SSC and SC arrays, each of the capacitors is modeled as the sum of the nominal capacitance value and the error term, as follows:


Consider the case where all the errors are in the unit capacitors whose values are independent-identically-distributed Gaussian random variables with a variance of

𝐸𝛿2𝑛,1𝛿=𝐸2𝑛,2=2𝑛1𝜎20,(5) and where 𝜎0 is the standard deviation of the unit capacitor.

The accuracy of an SAR ADC is dependent on the DAC outputs which are calculated here in the case of no initial charge on the array (𝑉in=0). For a given DAC digital input 𝑋, with 𝐷𝑛,𝑚 equals 1 or 0 representing the ADC decision for bit 𝑛, the analog output 𝑉out(𝑋) of the SSC array can be calculated as

𝑉out=(𝑋)2𝐶atten𝑏𝐿𝑛=12𝑚=1𝐷𝑛,𝑚𝐶𝑛,𝑚+𝑏𝑀1𝑛=12𝑚=1𝐷𝑛,𝑚𝐶𝑛,𝑚2𝐶atten𝐶totalLSB+𝐶totalMSB+𝐶totalLSB𝐶totalMSB𝑉+Δ𝐶ref+𝐶totalLSB+𝑏𝐿𝑛=12𝑚=1𝛿𝑛,𝑚𝑏𝑀1𝑛=12𝑚=1𝐷𝑛,𝑚𝐶𝑛,𝑚2𝐶atten𝐶totalLSB+𝐶totalMSB+𝐶totalLSB𝐶totalMSB𝑉+Δ𝐶ref(6) where

𝐶𝑛,𝑚=2𝑛1𝐶0+𝛿𝑛,𝑚,Δ𝐶=𝑏𝑀1𝑛=12𝑚=1𝛿𝑛,𝑚2𝐶atten+𝐶totalLSB+𝑏𝐿𝑛=12𝑚=1𝛿𝑛,𝑚2𝐶atten+𝐶totalMSB+𝑏𝑀1𝑛=12𝑚=1𝛿𝑛,𝑚.(7) Subtracting the nominal value (i.e., 𝛿𝑛,𝑚=0 in (6)) from (6) the INL can be calculated as

INLssc=2𝐶atten𝛿𝑋+𝛿𝑌+𝛿𝑌𝛿𝑋+𝐶totalLSB𝛿𝑌2𝐶atten𝐶totalLSB+𝐶totalMSB+𝐶totalLSB𝐶totalMSB𝑉+Δ𝐶ref+𝑏𝑀1𝑛=12𝑚=1𝐷𝑛,𝑚𝐶𝑛,𝑚𝛿𝑋2𝐶atten𝐶totalLSB+𝐶totalMSB+𝐶totalLSB𝐶totalMSB𝑉+Δ𝐶ref,𝛿𝑋=𝑏𝐿𝑛=12𝑚=1𝐷𝑛,𝑚𝛿𝑛,𝑚,𝛿𝑌=𝑏𝑀1𝑛=12𝑚=1𝐷𝑛,𝑚𝛿𝑛,𝑚,(8) The first and second terms are quite small when compared with the third and fourth terms in the numerator, and the third term ΔC in the denominator does not depend on the bit decision 𝐷𝑛,𝑚, which only causes a gain error; then they will be neglected. Thus, (8) can be simplified as

INLssc𝐶totalLSB𝛿𝑌+𝑏𝑀1𝑛=12𝑚=1𝐷𝑛,𝑚𝐶𝑛,𝑚𝛿𝑋2𝐶atten𝐶totalLSB+𝐶totalMSB+𝐶totalLSB𝐶totalMSB𝑉ref,(9) and the variance can be expressed as

𝐸INL2ssc=𝐶2totalLSB𝐸𝑏𝑀1,1+𝐸𝑏𝑀1,22𝐶atten𝐶totalLSB+𝐶totalMSB+𝐶totalLSB𝐶totalMSB2𝑉2ref+𝑏𝑀1𝑛=12𝑚=1𝐷𝑛,𝑚𝐶𝑛,𝑚2𝐸𝑏𝐿,1+𝐸𝑏𝐿,22𝐶atten𝐶totalLSB+𝐶totalMSB+𝐶totalLSB𝐶totalMSB2𝑉2ref,𝐸(10)𝑏𝑀1,1=𝐸𝑏𝑀1𝑛=1𝐷𝑛,1𝛿𝑛,12,𝐸𝑏𝑀1,2=𝐸𝑏𝑀1𝑛=1𝐷𝑛,2𝛿𝑛,22,𝐸𝑏𝐿,1=𝐸𝑏𝐿𝑛=0𝐷𝑛,1𝛿𝑛,12,𝐸𝑏𝐿,2=𝐸𝑏𝐿𝑛=0𝐷𝑛,2𝛿𝑛,22.(11) To simplify the analysis only the worse INL is considered that combines all the errors together (i.e., 𝐷𝑛,𝑚=1). For (5) it can be concluded that 𝐸𝑏𝑀1,1=𝐸𝑏𝑀1,2 and 𝐸𝑏𝐿,1=𝐸𝑏𝐿,2. Thus (10) can be simplified as

𝐸INL2ssc=2𝑏𝐿𝐶02𝑏𝑀1𝑛=12𝑛𝜎20+𝑏𝑀1𝑛=12𝑛1𝐶02𝑏𝐿𝑛=12𝑛𝜎20𝐶atten(2𝑏𝐿+1𝐶0+𝑏𝑀1𝑛=12𝑛𝐶0)+2𝑏𝐿𝐶0𝑏𝑀1𝑛=12𝑛𝐶02𝑉2ref.(12) While for the SC array, the 𝐸[INL2sc] can be calculated similarly as

𝐸INL2sc=2𝑏𝐿𝐶02𝑏𝑀𝑛=12𝑛1𝜎20𝐶atten(2𝑏𝐿𝐶0+𝑏𝑀𝑛=12𝑛1𝐶0)+2𝑏𝐿𝐶0𝑏𝑀𝑛=12𝑛1𝐶02𝑉2ref+𝑏𝑀𝑛=12𝑛1𝐶02𝑏𝐿𝑛=12𝑛1𝜎20𝐶atten(2𝑏𝐿𝐶0+𝑏𝑀𝑛=12𝑛1𝐶0)+2𝑏𝐿𝐶0𝑏𝑀𝑛=12𝑛1𝐶02𝑉2ref.(13) Then, subtracting (12) from (13), its value will become


As a result of (14), the INL of the SSC array should be lower than the SC array which is different from the BWC and BWSC arrays that were already proven to have no difference between the INLs [1].

The maximum DNL for the SSC array is expected to occur at the step below the MSB transition [1], and the two output voltages can be calculated as

𝑉err𝐶(𝑋)totalLSB𝑏𝑀1𝑛=1𝛿𝑛+𝑏𝑀1𝑛=12𝑛1𝐶0𝑏𝐿𝑛=12𝑚=1𝛿𝑛,𝑚2𝐶atten𝐶totalLSB+𝐶totalMSB+𝐶totalLSB𝐶totalMSB𝑉ref,𝑉(15)err𝐶(𝑋1)totalLSB𝑏𝑀2𝑛=12𝑚=1𝛿𝑛,𝑚2𝐶atten𝐶totalLSB+𝐶totalMSB+𝐶totalLSB𝐶totalMSB𝑉ref+𝑏𝑀2𝑛=12𝑛𝐶0𝑏𝐿𝑛=12𝑚=1𝛿𝑛,𝑚2𝐶atten𝐶totalLSB+𝐶totalMSB+𝐶totalLSB𝐶totalMSB𝑉ref,(16) subtracting (16) from (15), they will yield

DNLssc=2𝑏𝐿+1𝐶0𝛿𝑏𝑀1𝑏𝑀2𝑛=1𝛿𝑛,2+𝐶0𝑏𝐿𝑛=12𝑚=1𝛿𝑛,𝑚2𝐶atten𝐶totalLSB+𝐶totalMSB+𝐶totalLSB𝐶totalMSB𝑉2ref(17) with variance

𝐸DNL2ssc=2𝑏𝐿𝐶022𝑏𝑀2𝜎20𝑏𝑀2𝑛=12𝑛1𝜎20𝐶atten(2𝑏𝐿+1𝐶0+𝑏𝑀1𝑛=12𝑛𝐶0)+2𝑏𝐿𝐶0𝑏𝑀1𝑛=12𝑛𝐶02𝑉2ref+𝐶0𝑏𝐿𝑛=12𝑛1𝜎20𝐶atten(2𝑏𝐿+1𝐶0+𝑏𝑀1𝑛=12𝑛𝐶0)+2𝑏𝐿𝐶0𝑏𝑀1𝑛=12𝑛𝐶02𝑉2ref=2𝑏𝐿𝐶02+2𝐶0𝑏𝐿𝑛=12𝑛1𝜎202𝐶atten(2𝑏𝐿+1𝐶0+𝑏𝑀1𝑛=12𝑛𝐶0)+2𝑏𝐿𝐶0𝑏𝑀1𝑛=12𝑛𝐶02𝑉2ref.(18) For SC array the 𝐸[DNL2sc] can be calculated similarly as

𝐸DNL2sc=2𝑏𝐿𝐶02+𝐶0𝑏𝐿𝑛=12𝑛1𝜎20𝐶atten(2𝑏𝐿𝐶0+𝑏𝑀𝑛=12𝑛1𝐶0)+2𝑏𝐿𝐶0𝑏𝑀𝑛=12𝑛1𝐶02𝑉2ref;(19) thus, 𝐸[DNL2sc]/𝐸[DNL2ssc] can be expressed as

𝐸DNL2ssc𝐸DNL2sc2𝑏𝐿𝐶02+2𝐶0𝑏𝐿𝑛=12𝑛122𝑏𝐿𝐶02+𝐶0𝑏𝐿𝑛=12𝑛1<1.(20) Thus, from (20) it can be concluded that the maximum DNL of the SSC is also lower than that of the SC array.

3.4. Parasitic Nonlinearity Effect

One potential issue with these two series capacitor array structures (SSC and SC) is the parasitic capacitances 𝐶𝑝1 and 𝐶𝑝2 on the nodes 𝐴 and 𝐵, which will deteriorate the desired voltage division ratio and result in poor linearity. The parasitic effect is caused by the bottom- and top-plate parasitic capacitance of 𝐶atten as well as the top-plate parasitic capacitance of MSB and LSB array capacitors which can be calculated as

𝐶𝑝1=𝛼𝐶atten+𝛽𝐶sumMSB,𝐶𝑝2=𝛽𝐶atten+𝛽𝐶sumLSB,(21) where 𝛼 and 𝛽 represent the percentage of bottom- and top-plate parasitic capacitances of each capacitor, respectively (with metal-isolator-metal (MIM) capacitor option, 𝛼=10%, 𝛽=5%). For the SSC array, the analog output 𝑉out(𝑋) with 𝐶𝑝1 and 𝐶𝑝2 taken in to account can be calculated as

𝑉out=𝐶(𝑋)atten𝑏𝐿𝑛=12𝑛=1𝐷𝑛,𝑛2𝑛1𝐶0+𝑏𝑀𝑛=12𝑏=1𝐷𝑛,𝑛2𝑛1𝐶0𝐶atten𝐶sumLSB+𝐶sumMSB+𝐶𝑝1+𝐶𝑝2𝑉+𝔇ref+𝐶sumLSB+𝐶𝑝2𝑏𝑀𝑛=12𝑛=1𝐷𝑛,𝑛2𝑛1𝐶0𝐶atten𝐶sumLSB+𝐶sumMSB+𝐶𝑝1+𝐶𝑝2𝑉+𝔇ref,(22) where 𝔇 denotes (𝐶sumLSB+𝐶𝑝2)(𝐶sumMSB+𝐶𝑝1). This equation shows that the parasitic capacitances 𝐶𝑝1 and 𝐶𝑝2 in the denominator are completely uncorrelated in the bit decisions, which can cause only a gain error and have no effect into the linearity performance. However, the parasitic capacitance 𝐶𝑝2 in the numerator contributes with a code-dependent error, which degrades the linearity of the SAR ADC. Subtracting the nominal value the error term will become

𝑉error=𝐶(𝑋)𝑝2𝑏𝑀𝑛=12𝑛=1𝐷𝑛,𝑛2𝑛1𝐶0𝐶atten𝐶sumLSB+𝐶sumMSB+𝐶𝑝1+𝐶𝑝2𝑉+𝔇ref.(23) The parasitic capacitance 𝐶𝑝2 is composed of the parasitic capacitance of 𝐶atten and 𝐶sumLSB. By reducing the number of bits in the LSB array, the size of 𝐶sumLSB can be minimized; thus the nonlinearity effect can be alleviated. But, this will enlarge the capacitor spread in the MSB array; thus the distribution of bits in both MSB and LSB arrays should consider the trade-off between linearity, tolerance, and capacitance spread limitations.

3.5. Behavioral Simulations

Four behavioral simulations of the SSC and the SC array DAC were performed to verify the previous analysis. The values of the unit and attenuation capacitors used are Gaussian random variables with standard deviation of 1% (𝜎0/𝐶0=0.01), and the ADC is otherwise ideal. Figure 3 shows the result of 10000-time Monte Carlo runs, where the standard deviation of DNL and INL is plotted versus output code at the 8-bit level. As expected, the SSC array has better INL and DNL than its SC array counterpart. Figure 4 shows the result of 1000 Monte Carlo runs with 5% top-plate and 10% bottom-plate parasitic capacitances, where the SNDRs are plotted versus different distribution of bits in the MSB and LSB array at the 8-bit level. Comparing the SNDR shown in Figure 4, and as expected, a larger number of bits in the LSB array will cause poor linearity. Although MSBLSB=52 can achieve the best SNDR, since larger capacitor ratios will both reduce the conversion speed and increase the power dissipation, MSBLSB=43 will be adopted for circuit implementation due to both good linearity performance and smaller capacitor ratios. Figure 5 illustrates the result of 1000-time Monte Carlo runs, where the SNDRs are plotted versus the percentage of the top-plate parasitic capacitance 𝛽 for the SSC array structure for an 8-bit ADC. With 𝐶𝑝2 increasing, the parasitic capacitance will decrease the SNDR of the conversion performance. But with approximate ±5% variance of 𝛽 a good linearity performance of an SAR ADC can still be achieved. Figure 6 illustrates the result of 1000 Monte Carlo runs, where the SNDRs are plotted versus the percentage of the top-plate parasitic capacitance 𝛽 at the 6- to 12-bit level with proper bits distribution of the LSB and MSB arrays. From it we can find that the parasitic nonlinearity effect is insignificant; thus the series split structure can also be utilized in high-resolution applications.

3.6. Power Consumption Analysis

The power consumption of the SAR converter is dominated by the DAC capacitor array, the comparator, and the switches’ drivers. The array’s power is proportional to the sum of the array total capacitance 𝐶total of which the bottom-plate is connected to the reference voltage supply and can be calculated as

𝑃array=𝐶total𝑉ref𝑉FS(24) where 𝑉FS is the full-scale input voltage, assuming that 𝑉FS has been fully sampled on to the capacitor array and the charge is all supplied by the reference voltage 𝑉ref [1]. In a 8-bit case, the 𝐶total of the proposed structure is 46𝐶0 (with MSBLSB=43), but for a binary-weighted capacitor array the 𝐶total is 256𝐶0, which can consume 5 times more power than the proposed structure. The series combination allows a significant reduction of the largest capacitor ratio; in an 8-bit case, the largest capacitor 𝐶max of the series split and binary-weighted split capacitor array structure is 8𝐶0 and 64𝐶0, respectively, which decreases the DAC settling time and speeds up the conversion. The total input capacitance of the proposed structure is not completely dependent on the number of bits of the ADC and can be calculated as


The power consumptions of the comparator and switch drivers are also proportional to the equivalent input capacitance 𝐶in. Therefore, the smaller 𝐶total, 𝐶max, and 𝐶in it will imply an increase in efficiency of the overall conversion performance.

4. Circuit Implementation Details

A high-speed SAR converter imposes a stringent requirement in the clock generation; for example, an 8 b 180 MS/s SAR ADC requires an internal master clock of over 1.62 GHz. To generate such a high-frequency clock pulse the generator will consume even more power than the ADC itself. Due to the power limitations of the clock generator in a synchronous SA design an asynchronous SAR processing technique [4] will be adopted here, where only a master clock of 180 MHz is required.

The dynamic comparator [6] used in this ADC is shown in Figure 7 and it is composed of a preamplifier and a regenerative latch. The preamplifier can provide sufficient gain to suppress the relatively high input referred offset voltage of the latch. Also, the kickback noise of the latch can be isolated by the current mirror between the two stages. The dynamic operation of this circuit is divided into a reset phase and a regeneration phase. During the reset phase the two outputs (𝑉op and 𝑉on) are pulled up to 𝑉DD. After the input stage has settled, the voltage difference is then amplified to a full swing during the regeneration phase. The differential output can generate a data ready signal to indicate the completion of the comparison, which will be used to trigger a sequence of shift registers and the switch drivers to perform asynchronous conversion [4]. Dynamic logic circuits are also utilized instead of traditional static logic to release the limitation of digital feedback propagation delay in the SA loop.

5. Simulation of an 8-Bit 180 MS/s SAR ADC

To verify the proposed capacitor structure of the capacitive DAC, a 1.2 V, 8 b, 180-MS/s SAR ADC was designed using a 90 nm CMOS process with metal-isolator-metal (MIM) capacitor option. The SAR ADC was implemented in a fully differential architecture, with a full scale differential input range of 1.2 𝑉PP. Considering the parasitic capacitance of the attenuation capacitors that will reduce the linearity of the ADC, 5% top-plate and 10% bottom-plate, they were included in the simulations according to the data from the foundry datasheet.

Figure 8 shows a spectrum plot of the SAR ADC after a Monte Carlo simulation with an input signal of 76 MHz leading to an SNDR of 48 dB, which clearly demonstrates the tolerance to the parasitic effect caused by the 𝐶𝑝2. Figure 9 also shows the corresponding 30-times Monte Carlo mismatch simulations where the ADC achieves a mean SNDR of 49 dB with an input signal of 76 MHz. The DNL and INL are both within ±0.5LSB as shown in Figure 10. Figure 11 shows the SNDR versus power consumption from the reference ladder in the proposed architecture, as well as in the BWSC array structure, clearly demonstrating that the BWSC results are poor in terms of SNDR mainly due to the large RC settling time. To reach the same conversion performance the BWSC array consumes 10 times more power than the proposed structure. Table 1 summarizes the overall performance of the SAR ADC with the total power consumption of 14 mW only and an FoM of 0.37 pJ/conversion-step, distinctly proving the low power dissipation feature of the proposed technique.

6. Conclusions

A novel series-split capacitive DAC technique has been proposed which can both implement an efficient charge recycling SAR operation and achieve a small input capacitance. The reduction of the maximum ratio and sum of the total capacitance can lead to area savings and power efficiency, which allow the SAR converter to work at high speed while meeting a low power consumption requirement. Theoretical analysis and behavioral simulations of the linearity performance demonstrate that the proposed SSC structure can have a better INL and DNL than the traditional SC array structure. Simulation results of a 1.2 V, 8 b, 180-MS/s SAR ADC were presented exhibiting an SNDR of 48 dB at a 76 MHz input with the total power consumption of 14 mW that certifies the power efficiency of the novel circuit structure.


This work was financially supported by research grants from the University of Macau and FDCT with Ref nos. RG-UL/07-08S/Y1/MR01/FST and FDCT/009/2007/A1.