VLSI Design

VLSI Design / 2010 / Article / Fig 5

Research Article

Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs

Figure 5

Behavioral simulation of 1000 Monte Carlo SNDR versus the percentage of the top-plate parasitic capacitance β for the SSC array at 8 bit level.

We are committed to sharing findings related to COVID-19 as quickly and safely as possible. Any author submitting a COVID-19 paper should notify us at help@hindawi.com to ensure their research is fast-tracked and made available on a preprint server as soon as possible. We will be providing unlimited waivers of publication charges for accepted articles related to COVID-19.