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Research Article

Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs

Table 1

Performance Summary of the SAR ADC.

Technology90-nm CMOS with MIM

Resolution8 bit
Sampling Rate180 MS/s
Supply Voltage1.2 V
Full Scale Analog Input1.2 Vpp differential
SNDR (@fin=76MHz)48 dB
SFDR (@fin=76MHz)58 dB
ENOB (@fin=76MHz)7.7 bit
FOM0.37 pJ/conversion step
DNL±0.5 LSB
INL±0.5 LSB

Power Consumption
Analog9.4 mW
Digital2.3 mW
Reference ladder2.3 mW
Total14 mW

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