VLSI Design

VLSI Design / 2010 / Article / Tab 2

Review Article

CORDIC Architectures: A Survey

Table 2

Comparison of various rotational CORDIC architectures, (SD: signed digit, CS: carry save).

Method (year) Radix, ρ Arithmetic Latency (tFA) Iterative Iterative Scale factor
Nonpipelined PipelinedX/Y pathZ-pathK

Nonredundant (1959) [3]2 2's complimentn2n2 Constant
Redundant (1987) [42]2 CSntstagentstage Variable
Double-rotation/2 SD1.5ntstage1.5ntstage Constant
Correcting (1991) [51]
Low latency (1992) [55]2 CS(n+log3n-1)tstage((9n-3)/8)tstage Constant
Branching (1993) [52]2 SDntstagentstage Constant
DCORDIC (1996) [56]2 SD/CS(ntstage+n+1) Constant
Radix-4 (1993) [58]4 SD(3n/4+1)tstage Variable
Radix2-4 (1996) [59]24 CS(3n/4+1)tstage Constant
Radix-4 (1997) [43]4 CS(2n/3+1)tstagen/6 Variable
PCORDIC (2002) [61]2 SD(1.7n+1.25+log2n)× Constant
Flat CORDIC (2002) [63]2 SD 34 for 16-bit, 50 for 32-bit combinational×Constant
Para-CORDIC (2004) [64]2 CS(2(s(n)+n/2-l+2)+log1.5n+2)× Constant
Semi-flat (2006) [65]2 SD 33 for 16-bitλ/combinationalλ Constant
Nonredundant low-latency (2008) [49]2 2's compliment(n/2+2)tadder + tmultiplier(n/2+1)/multipliern/3 Constant

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