VLSI Design

VLSI Design / 2010 / Article / Tab 2

Research Article

A Pipelined and Parallel Architecture for Quantum Monte Carlo Simulations on FPGAs

Table 2

BlockRAM Usage by the Lookup Tables.

BlockPosBlockPEBlockWF

x/(a1 and a2)16 KB (8)18 KB (10)18 KB (10)
y/(b1 and b2)16 KB (8)18 KB (10)18 KB (10)
z/(c1 and c2)16 KB (8)18 KB (10)18 KB (10)

Total48 KB (24)54 KB (30)54 KB (30)