Table of Contents
VLSI Design
Volume 2011, Article ID 178516, 19 pages
Review Article

Advancement in Nanoscale CMOS Device Design En Route to Ultra-Low-Power Applications

1Department of Information Technology, VLSI Design Laboratory, ABV-Indian Institute of Information Technology and Management, Madhya Pradesh, Gwalior 474010, India
2School of Studies in Physics, Jiwaji University, Madhya Pradesh, Gwalior 474011, India

Received 9 September 2010; Revised 11 January 2011; Accepted 11 March 2011

Academic Editor: A. G. M. Strollo

Copyright © 2011 Subhra Dhar et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


In recent years, the demand for power sensitive designs has grown significantly due to the fast growth of battery-operated portable applications. As the technology scaling continues unabated, subthreshold device design has gained a lot of attention due to the low-power and ultra-low-power consumption in various applications. Design of low-power high-performance submicron and deep submicron CMOS devices and circuits is a big challenge. Short-channel effect is a major challenge for scaling the gate length down and below 0.1 μm. Detailed review and potential solutions for prolonging CMOS as the leading information technology proposed by various researchers in the past two decades are presented in this paper. This paper attempts to categorize the challenges and solutions for low-power and low-voltage application and thus provides a roadmap for device designers working in the submicron and deep submicron region of CMOS devices separately.