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VLSI Design
/
2011
/
Article
/
Fig 19
/
Review Article
Advancement in Nanoscale CMOS Device Design En Route to Ultra-Low-Power Applications
Figure 19
𝑉
t
h
roll-off quantified by change in
𝑉
t
h
between
𝐿
−
and
𝐿
+
devices with drain biased at
𝑉
d
d
[
26
].