Device performance deteriorates due to polydepletion effects as devices scale down
Polydepletion effects
Using less dopant gradient Highly doped gates
Vertically nonuniform and steep dopant profile in polygate result in built electric field effect and potential drops in the gate region. Laterally nonuniform and convex dopant profiles in the polygate cause substantial edge pot. drops for short
Control of gate-leakage current is paramount inlow-power CMOS circuit design
Reduce gate currents
Between the high-k layer and silicon substrate an interfacial oxide layer is present, and a transition layer between high-k dielectric and silicon substrate may exist High-k gate stack
The gate current is reduced by the addition of a transition layer and with increasing thickness of the transition layer for the same EOT
Pot. Barrier lowering both in the inversion channel and in the body depletion region
adjustment, body punch-through
Angle tilted implantation Superhalo and a retrograde channel
Good / performance achieved for both n-p channel devices, excellent control of roll-off down to 40 nm , 935 μA/μm, 395 μA/μm on-state drive currents with of 1.5 V