Review Article

Advancement in Nanoscale CMOS Device Design En Route to Ultra-Low-Power Applications

Table 2

Roadmap for submicron CMOS devices.

Range of
operation
Performance factorsChallengesTechnique/SolutionEnhanced performanceApplications

Sub-100 nmElevated off-state leakage due to lowering of 𝑉 t h under tech. scalingReduce leakage currentsLowering of temperature
Cooling solutions
Total leakage current may be reduced by more than 200x by cooling from 127°C to 0°CLOP [36]

Sub-100 nmDevice performance deteriorates due to polydepletion effects as devices scale downPolydepletion effectsUsing less dopant gradient
Highly doped gates
Vertically nonuniform and steep dopant profile in polygate result in built electric field effect and potential drops in the gate region. Laterally nonuniform and convex dopant profiles in the polygate cause substantial edge pot. drops for short L g s LSTP [34]

Sub-100 nm 𝑉 t h lowering in short channel regionSubthreshold swing, reduced electric field at the drainOptimizing junction depths and channel doping
Grooved gate MOSFET
𝑉 t h lowering not observed even beyond 0.1 m due to corner effect, 𝑉 t h increases for shorter L for grooved gate MOSFETsLOP [37]

Sub-100 nmControl of gate-leakage current is paramount inlow-power CMOS circuit designReduce gate currentsBetween the high-k layer and silicon substrate an interfacial oxide layer is present, and a transition layer between high-k dielectric and silicon substrate may exist
High-k gate stack
The gate current is reduced by the addition of a transition layer and with increasing thickness of the transition layer for the same EOTLOP [9]

Sub-100 nmAdverse 𝑉 t h roll off 𝑉 t h roll off controlIon implantation
Pocket implant
Pocket implant device through optimization of k parameter pushes 𝐿 m i n to 55–60% of that of UD channel device, 𝑉 t h overshoots 100 mVHP-LOP [38]

Sub-100 nmHigh bulk impurity conc. leads to an increase in 𝑉 t h Reduce 𝑉 t h Low-doped zone next to high-doped substrate
Stepped doping profile
Higher mobility and lower threshold voltage, Δ 𝑉 t h = 0 . 5 V HP [25]

Sub-70 nmPot. Barrier lowering both in the inversion channel and in the body depletion region 𝑉 t h adjustment, body punch-throughAngle tilted implantation
Superhalo and a retrograde channel
Good 𝐼 d r i v e / 𝐼 O F F performance achieved for both n-p channel devices, excellent control of 𝑉 t h roll-off down to 40 nm 𝐿 g , 935 μA/μm, 395 μA/μm on-state drive currents with 𝑉 d d of 1.5 VHP-LOP [37]