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VLSI Design
Volume 2011 (2011), Article ID 475952, 17 pages
http://dx.doi.org/10.1155/2011/475952
Research Article

A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies

1Institute of Radio Physics and Electronics, University of Calcutta, Kolkata 700009, India
2Indian Institute of Technology, Kharagpur 721302, India

Received 4 March 2011; Accepted 28 May 2011

Academic Editor: Sheldon Tan

Copyright © 2011 Soumya Pandit et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Soumya Pandit, Chittaranjan Mandal, and Amit Patra, “A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies,” VLSI Design, vol. 2011, Article ID 475952, 17 pages, 2011. doi:10.1155/2011/475952