Research Article

A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies

Table 10

Transistor sizes and feasibility constraints for preamplifier.

Transistor sizesGeometry constraints
𝐺 𝑚 1 𝐺 𝑚 2

𝑊 1 = 𝑊 2 ( 2 8 0 n m , 4 0 0 𝜇 m ) ( 2 8 0 n m , 2 0 0 𝜇 m )
𝑊 3 = 𝑊 4 = 𝑊 6 = 𝑊 7 ( 1 𝜇 m , 2 0 𝜇 m ) ( 1 𝜇 m , 2 0 𝜇 m )
𝑊 8 = 𝑊 9 ( 2 8 0 n m , 1 0 𝜇 m ) ( 2 8 0 n m , 1 0 𝜇 m )
𝐼 b i a s ( 1 𝜇 A , 4 0 𝜇 A ) ( 1 𝜇 A , 1 0 𝜇 A )

Parameters Range
Functional constraints 𝑉 g s 𝑉 t h ≥0.1 V
𝑉 o p 0.9 V
𝑉 o f f ≤2 mV

Performance constraints Input linearity ≥15 mV
Swing ≥750 mV
Bandwidth ≥2 MHz
Phase margin ( 4 5 , 6 0 )