Table of Contents
VLSI Design
Volume 2011, Article ID 530851, 10 pages
Research Article

Buffer Planning for IP Placement Using Sliced-LFF

1Tsinghua National Laboratory for Information Science & Technology, Tsinghua University, Beijing 100084, China
2Information, Production and Systems (IPS), Waseda University, Kitakyushu-shi 808-0135, Japan

Received 14 November 2010; Accepted 11 December 2010

Academic Editor: Shiyan Hu

Copyright © 2011 Ou He et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


IP cores are widely used in modern SOC designs. Hierarchical design has been employed for the growing design complexity, which stimulates the need for fixed-outline floorplanning. Meanwhile, buffer insertion is usually adopted to meet the timing requirement. In this paper, buffer insertion is considered with a fixed-outline constraint using Less Flexibility First (LFF) algorithm. Compared with Simulated Annealing (SA), our work is able to distinguish geometric differences between two floorplan candidates, even if they have the same topological structure. This is helpful to get a better result for buffer planning since buffer insertion is quite sensitive to a geometric change. We also extend the previous LFF to a more robust version called Sliced-LFF to improve buffer planning. Moreover, a 2-staged LFF framework and a post-greedy procedure are introduced based on our net-classing strategy and finally achieve a significant improvement on the success rate of buffer insertion (40.7% and 37.1% in different feature sizes). Moreover, our work is much faster than SA, since it is deterministic without iterations.