VLSI Design

VLSI Design / 2011 / Article / Tab 1

Research Article

Vertical Gate RF SOI LIGBT for SPICs with Significantly Improved Latch-Up Immunity

Table 1

All parameters and symbols in Figure 8.

𝑉 d d Power supply 𝑅 d e Resistance of drift region for electron current

𝑍 𝐿 Load impedance 𝑅 n b Resistance of n-buffer region

𝑉 g s Bias voltage between gate and source electrodes 𝑅 p p Resistance of pinched P-well region

G n d Ground 𝑅 d h Resistance of drift region for hole current

𝑀 𝑉 VG MOSFET 𝑇 𝐿 Lateral transistor

𝑇 𝑉 Vertical transistor 𝑉 d s Output