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VLSI Design
Volume 2011, Article ID 756561, 8 pages
http://dx.doi.org/10.1155/2011/756561
Research Article

Weighted Transition Based Reordering, Columnwise Bit Filling, and Difference Vector: A Power-Aware Test Data Compression Method

1PG (VLSI Design), Nirma University, Ahmedabad 382481, India
2Indian Institute of Space Science & Technology, Tiruvanthapuram, India

Received 29 March 2011; Revised 14 May 2011; Accepted 29 July 2011

Academic Editor: Yangdong Deng

Copyright © 2011 Usha Mehta et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Usha Mehta, K. S. Dasgupta, and N. M. Devashrayee, “Weighted Transition Based Reordering, Columnwise Bit Filling, and Difference Vector: A Power-Aware Test Data Compression Method,” VLSI Design, vol. 2011, Article ID 756561, 8 pages, 2011. https://doi.org/10.1155/2011/756561.