Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints

<table>Uniform versus. Optimal downsizing. Linear downsizing of an inverter chain in order to save energy by increasing the delay results in a nonoptimal design—in this case 7% more energy could be saved by tuning the sizing correctly.</table>

VLSI Design

fig7

Figure 7

Figure 7: Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints 