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VLSI Design
Volume 2011 (2011), Article ID 896241, 9 pages
Research Article

Wirelength Minimization in Partitioning and Floorplanning Using Evolutionary Algorithms

1Department of Electronics and Communication, M. V. J. College of Engineering, Bangalore 560067, India
2Vivekanandha College of Engineering for Women, Trichengode 637205, Tamilnadu, India

Received 16 December 2010; Revised 23 April 2011; Accepted 6 July 2011

Academic Editor: Zhuo Li

Copyright © 2011 I. Hameem Shanavas and Ramaswamy Kannan Gnanamurthy. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Minimizing the wirelength plays an important role in physical design automation of very large-scale integration (VLSI) chips. The objective of wirelength minimization can be achieved by finding an optimal solution for VLSI physical design components like partitioning and floorplanning. In VLSI circuit partitioning, the problem of obtaining a minimum delay has prime importance. In VLSI circuit floorplanning, the problem of minimizing silicon area is also a hot issue. Reducing the minimum delay in partitioning and area in floorplanning helps to minimize the wirelength. The enhancements in partitioning and floorplanning have influence on other criteria like power, cost, clock speed, and so forth. Memetic Algorithm (MA) is an Evolutionary Algorithm that includes one or more local search phases within its evolutionary cycle to obtain the minimum wirelength by reducing delay in partitioning and by reducing area in floorplanning. MA applies some sort of local search for optimization of VLSI partitioning and floorplanning. The algorithm combines a hierarchical design technique like genetic algorithm and constructive technique like Simulated Annealing for local search to solve VLSI partitioning and floorplanning problem. MA can quickly produce optimal solutions for the popular benchmark.