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VLSI Design
Volume 2011 (2011), Article ID 896241, 9 pages
http://dx.doi.org/10.1155/2011/896241
Research Article

Wirelength Minimization in Partitioning and Floorplanning Using Evolutionary Algorithms

1Department of Electronics and Communication, M. V. J. College of Engineering, Bangalore 560067, India
2Vivekanandha College of Engineering for Women, Trichengode 637205, Tamilnadu, India

Received 16 December 2010; Revised 23 April 2011; Accepted 6 July 2011

Academic Editor: Zhuo Li

Copyright © 2011 I. Hameem Shanavas and Ramaswamy Kannan Gnanamurthy. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [4 citations]

The following is the list of published articles that have cited the current article.

  • U Akshata, “Simulation Model for Switching of Mobile Base Station,” International Journal of Information and Electronics Engineering, 2012. View at Publisher · View at Google Scholar
  • Kishore Kumar Muchherla, Jai Ganesh Kumar, and Janet M. Wang Roveda, “Cluster based dynamic area-array I/O planning for flip chip technology,” Microelectronic Engineering, 2013. View at Publisher · View at Google Scholar
  • I. Hameem Shanavas, and R. K. Gnanamurthy, “Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm,” Mathematical Problems in Engineering, vol. 2014, pp. 1–15, 2014. View at Publisher · View at Google Scholar
  • Jayanthi, Sivasubramanian, and Gunavathi, “Chip area minimization with voltage-island and fixed-outline constraints using dual level meta-heuristic optimization algorithms,” Journal of Computational and Theoretical Nanoscience, vol. 13, no. 7, pp. 4427–4438, 2016. View at Publisher · View at Google Scholar