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VLSI Design
Volume 2011 (2011), Article ID 896241, 9 pages
http://dx.doi.org/10.1155/2011/896241
Research Article

Wirelength Minimization in Partitioning and Floorplanning Using Evolutionary Algorithms

1Department of Electronics and Communication, M. V. J. College of Engineering, Bangalore 560067, India
2Vivekanandha College of Engineering for Women, Trichengode 637205, Tamilnadu, India

Received 16 December 2010; Revised 23 April 2011; Accepted 6 July 2011

Academic Editor: Zhuo Li

Copyright © 2011 I. Hameem Shanavas and Ramaswamy Kannan Gnanamurthy. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

I. Hameem Shanavas and Ramaswamy Kannan Gnanamurthy, “Wirelength Minimization in Partitioning and Floorplanning Using Evolutionary Algorithms,” VLSI Design, vol. 2011, Article ID 896241, 9 pages, 2011. doi:10.1155/2011/896241