Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design

Table 2

Switching voltage at output node 𝑉 of the capacitance network.

Inputs			Voltage at 𝑉 node	Majority Not
𝐴	𝐵	𝐶	𝑉DD	Carry
0	0	0	0V	1
0	0	1	𝑉DD/3	1
0	1	0	𝑉DD/3	1
0	1	1	2𝑉DD/3	0
1	0	0	𝑉DD/3	1
1	0	1	2𝑉DD/3	0
1	1	0	2𝑉DD/3	0
1	1	1	𝑉DD	0