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VLSI Design
/
2012
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Article
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Tab 1
/
Research Article
A Novel Framework for Applying Multiobjective GA and PSO Based Approaches for Simultaneous Area, Delay, and Power Optimization in High Level Synthesis of Datapaths
Table 1
Comparison of WSGA and power-aware WSGA.
Benchmark
WSGA without power optimization [
2
]
Power-aware WSGA
Reduction in power cost metric
Power metric
Area
(register units)
Delay
(time steps)
Power metric
Area
(register units)
Delay
(time steps)
IIR
0.9062
42.9
5.44
0.8996
48.48
5.15
0.73%
HAL
0.9911
38.33
4.74
0.8719
37.81
4.98
12%
FIR
0.6487
42.73
11.63
0.6029
54.48
11.32
7%
MPEG
0.6317
81.5
8.50
0.6046
107.5
9.00
17%