Automatic Generation of Optimized and Synthesizable Hardware Implementation from High-Level Dataflow Programs

<table class="table-group" width="800px"><tr class="fig-image" id="a"><td><img alt="298396.fig.004a" src="https://static.hindawi.com/articles/vlsi/volume-2012/298396/figures/298396.fig.004a.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(a) </b>SW-oriented definition  </td></tr></table></td></tr><tr class="fig-image" id="b"><td><img alt="298396.fig.004b" src="https://static.hindawi.com/articles/vlsi/volume-2012/298396/figures/298396.fig.004b.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(b) </b>HW-oriented definition </td></tr></table></td></tr></table>

<table>Two-way definition example of sum-5 actor behavior.</table>

VLSI Design

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Figure 4

Figure 4: Automatic Generation of Optimized and Synthesizable Hardware Implementation from High-Level Dataflow Programs 