Research Article
Automatic Generation of Optimized and Synthesizable Hardware Implementation from High-Level Dataflow Programs
Table 5
IDCT2D area consumption.
| Criterion | Xilinx design | Transformed design | Optimized design | VHDL design |
| Slice flip flops | 1415/55296 (2%) | 4002/55296 (7%) | 2113/55296 (3%) |
*
| Occupied slices | 1308/27648 (4%) | 5238/27648 (18%) | 2523/27648 (9%) | 3571/27648 (12%) | 4 input LUTs | 2260/55296 (4%) | 9861/55296 (17%) | 4777/55296 (8%) | 4640/55296 (8%) | Bonded IOBs | 48/489 (9%) | 49/489 (10%) | 49/489 (10%) |
*
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*Not mentioned in the literature.
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