A Graph-Based Approach to Optimal Scan Chain Stitching Using RTL Design Descriptions

Algorithm 2

VHDL process enriched with scan code.

process(clock)

begin

 if clock’ event and clock=‘1’ then

  if scan_en=‘1’ then

   𝐘<=𝐗;

   𝐙<=𝐘;

  else

   𝑍<=𝑋 or Y;

   𝑌<=𝑋 and Y;

  end if;

 end if;

end process;