A Graph-Based Approach to Optimal Scan Chain Stitching Using RTL Design Descriptions

Table 4

Fault coverage for RTL scan.

Design name	Fault coverage
ITC 99 Benchmarks (VHDL)
b09	99.86%
b10	99.85%
b11	99.93%
b12	99.97%
b13	99.92%
b14	99.99%
b15	99.97%
b17	99.47%
b18	99.81%
b19	99.81%
Opencore designs (Verilog)
Simple Spi	98.35%
Biquad	99.96%
Ac-97	99.80%