Homogeneous and Heterogeneous MPSoC Architectures with Network-On-Chip Connectivity for Low-Power and Real-Time Multimedia Signal Processing

Table 3

Comparison of the proposed MPSoCs versus the state of the art (all in 45 nm technology node except Tile64 in 90 nm CNOS and AsAP2 in 65 nm CMOS).

Processor	Area	Tr. count	Power	CMOS Tech.	Computational Power	Encoder supported/format
Het. MPSoC	49 mm^2	120 M	1 W	45 nm	1.5 GOPS + 128 G AD/s	H264/AVC video codec, HD
Hom. MPSoC	56 mm^2	150 M	2.8 W	45 nm	2.2 GOPS + 20 GFLOPS (extended-precision)	H264/AVC video codec, HD
CELL-BE [20]	115 mm^2	320 M	40 W	45 nm SOI	200 GFLOPS (single-precision)	H264/AVC video codec, HD
Core2 [34]	107 mm^2	290 M	44 W	45 nm	22 GOPS at 2.4 GHz	3D DCT codec, VGA
AsAP2 [42]	40 mm^2	55 M	10.5 W	65 nm	196.8 GMAC/s + 15 G AD/s + 680 M FFT-sample/s	H264/AVC video codec, HD
ATOM 330 [58]	52 mm^2	94 M	<8 W	45 nm	3.8 GOPS at 1.6 GHz	H264/AVC video codec, CIF
ATOM 230	26 mm^2	47 M	<4 W	45 nm	7.6 GOPS at 1.6 GHz	H264/AVC video codec, QCIF
Tile64 [44]	430 mm^2	615 M	11 W	90 nm	144 GOPS at 750 MHz	H264/AVC video codec, HD