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VLSI Design
Volume 2012 (2012), Article ID 505983, 13 pages
Research Article

Modeling and Design of a Nano Scale CMOS Inverter for Symmetric Switching Characteristics

1A. K. Choudhury School of Information Technology, University of Calcutta, Kolkata 700009, India
2Institute of Radio Physics and Electronics, University of Calcutta, Kolkata 700009, India

Received 12 October 2011; Revised 11 January 2012; Accepted 26 January 2012

Academic Editor: Chien-In Henry Chen

Copyright © 2012 Joyjit Mukhopadhyay and Soumya Pandit. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


This paper presents a technique for the modeling and design of a nano scale CMOS inverter circuit using artificial neural network and particle swarm optimization algorithm such that the switching characteristics of the circuit is symmetric, that is, has nearly equal rise and fall time and equal output high-to-low and low-to-high propagation delay. The channel width of the transistors and the load capacitor value are taken as design parameters. The designed circuit has been implemented at the transistor-level and simulated using TSPICE for 45 nm process technology. The PSO-generated results have been compared with SPICE results. A very good accuracy has been achieved. In addition, the advantage of the present approach over an existing approach for the same purpose has been demonstrated through simulation results.