Modeling and Design of a Nano Scale CMOS Inverter for Symmetric Switching Characteristics

Table 4

Delay constraints and design parameter bounds.

Case Study	𝐶𝐿(pF)	𝑊𝑛(nm)	𝑊𝑝(nm)	𝜏𝐹(ns)	𝜏𝑅(ns)	𝜏PHL(ns)	𝜏PLH(ns)
1	0.5–2.5	45–135	90–940	0.1–15	0.1–15	0.05–8.0	0.05–8.0
2	0.5–2.5	45–110	90–620	0.1–15	0.1–15	0.05–8.0	0.05–8.0
3	0.5–1.5	45–135	90–940	0.1–15	0.1–15	0.05–8.0	0.05–8.0
4	1.0–3.0	60–160	160–945	0.1–15	0.1–15	0.05–8.0	0.05–8.0
5	1.5–3.5	60–135	135–840	0.1–15	0.1–15	0.05–8.0	0.05–8.0
6	0.3–2.0	45–90	90–540	0.1–8.0	0.1–8.0	0.05–6.0	0.05–6.0
7	0.6–1.9	60–160	135–910	0.1–7.5	0.1–7.5	0.05–5.5	0.05–5.5