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VLSI Design
Volume 2012 (2012), Article ID 546212, 7 pages
http://dx.doi.org/10.1155/2012/546212
Research Article

Design of an All-Digital Synchronized Frequency Multiplier Based on a Dual-Loop (D/FLL) Architecture

Department of Electrical and Electronics Engineering, University Technology of PETRONAS (UTP), Perak, 31750 Tronoh, Malaysia

Received 2 March 2012; Revised 18 May 2012; Accepted 22 May 2012

Academic Editor: Antonio G. M. Strollo

Copyright © 2012 Maher Assaad and Mohammed H. Alser. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [2 citations]

The following is the list of published articles that have cited the current article.

  • Maher Assaad, Mohammed H. Alser, and Amine Bermak, “Design and characterization of low power and low noise truly all-digital clock and data recovery circuit for SERDES devices,” Journal of Low Power Electronics, vol. 9, no. 1, pp. 63–72, 2013. View at Publisher · View at Google Scholar
  • Mohammed H. Alser, Maher M. Assaad, and Fawnizu A. Hussin, “A wide-range programmable frequency synthesizer based on a finite state machine filter,” International Journal of Electronics, vol. 100, no. 11, pp. 1546–1556, 2013. View at Publisher · View at Google Scholar